The invention is in the field of Semiconductor-On-Insulator (SOI) devices, and relates more particularly to lateral SOI devices suitable for high-voltage applications.
In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, "on" resistance and manufacturing simplicity and reliability. Frequently, improving one parameter, such as breakdown voltage, will result in the degradation of another parameter, such as "on" resistance. Ideally, such devices would feature superior characteristics in all areas, with a minimum of operational and fabrication drawbacks.
One particularly advantageous form of SOI device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral MOSFET on the buried insulating layer, the MOSFET including a semiconductor surface layer on the buried insulating layer and having a source region of a first conductivity type, a channel region of a second conductivity type opposite to that of the first, an insulated gate electrode over the channel region and insulated therefrom, a lateral drift region of the first conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region.
A device of this type is shown in FIG. 1 common to related U.S. Pat. No. 5,246,870 (directed to a method) and U.S. Pat. No. 5,412,241 (directed to a device), commonly-assigned with the instant application and incorporated herein by reference. The device shown in FIG. 1 of the aforementioned patents is a lateral SOI MOSFET device having various features, such as a thinned SOI layer with a linear lateral doping region and an overlying field plate, to enhance operation. As is conventional, this device is an n-channel or NMOS transistor, with n-type source and drain regions, manufactured using a process conventionally referred to as NMOS technology.
More advanced techniques for enhancing high-voltage and high-current performance parameters of SOI power devices are shown in U.S. patent application Ser. No. 08/998,048, filed Dec. 24, 1997, commonly-assigned with the instant application and incorporated herein by reference. Yet another technique for improving the performance of a semiconductor power switch is to form a hybrid device, which combines more than one type of device into a single structure. Thus, for example, in U.S. Pat. No. 4,939,566, commonly-assigned with the instant application and incorporated herein by reference, a semiconductor switch is disclosed which is fabricated in a bulk semiconductor substrate and includes a lateral DMOS transistor and a lateral IGT in the same structure.
Thus, it will be apparent that numerous techniques and approaches have been used in order to enhance the performance of power semiconductor devices, in an ongoing effort to attain a more nearly optimum combination of such parameters as breakdown voltage, size, current-carrying capability and manufacturing ease.
In particular, circuit applications which require a source-follower configuration operating at high voltage with significant source-follower current flow present substantial challenges to device designers. Once advantageous approach to providing an SOI MOSFET device suitable for source-follower operation is disclosed in U.S. patent application Ser. No. 09/100,832, entitled LATERAL THIN-FILM SOI DEVICES WITH GRADED TOP OXIDE AND GRADED DRIFT REGION, filed Jun. 19, 1998, commonly-assigned with the instant application and incorporated herein by reference. While all of the foregoing structures provide varying levels of improvement in device performance, no one device or structure fully optimizes all of the design requirements for high-voltage, high-current operation, particularly in the source-follower mode.
Accordingly, it would be desirable to have a transistor device structure capable of high performance in a high-voltage, high-current environment, and which is particularly suitable for source-follower circuit applications in such an environment.